Systolic Array Sorting Engine

This post demonstrates the implementation of a systolic array based sorting engine, which consists of 8 processors containing 2 elements each, for a total of 16 elements to be sorted. This project was part of an IIT Madras course titled “Mapping DSP Algorithms to Architectures”, co-taught by Prof. Nitin Chandrachoodan of IIT Madras and Prof. CP…

Building a JPEG Compression Engine – II

This is a follow-up to the previous post on building a JPEG Compression Engine. This post assumes some background with the Xilinx Zynq All Programmable System on Chip (APSoC) series. In this post, the code was directly converted to C from Python by adding data types and libraries wherever necessary. The image was read from…